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05/01/2001

Thermal Budgets

[Bortrum is on vacation and will return May 15]

Having just filed your tax returns in April, some of you may be
thinking about the need to go on a stricter budget. If so, you''re
not alone. The silicon chip community is and has been quite
concerned about their "thermal budgets" for some time. So, let''s
switch from the ultimate frigidity of recent columns to hotter
stuff. As with the frigid columns, this column was inspired by a
lecture at the recent meeting of The Electrochemical Society
(ECS) in Washington. This was the Solid State Science and
Technology award lecture presented by Arnold Reisman. The
title of his talk was pretty technical but his subtitle was more
down to earth - "The Road to Smallness is Strewn with
Tolerances".

Arnie was one of the first physical scientists hired by IBM back
in 1953 when IBM was setting up their T. J. Watson Research
center in New York City. This was at the beginning of the era of
the semiconductor revolution and I''ve known him for many
decades. In fact, I almost became a colleague of his in IBM''s
then newly built Yorktown Heights research center. During a
brief period of some discontent at Bell Labs, I received an offer
from IBM but turned it down and remained with Bell.

Arnie''s "road to smallness" is the road that has led to the ever
increasing number of transistors on a silicon chip following a law
never passed by a legislative body. That law, of course, is the
famed Moore''s Law that says the number of transistors on the
chip will double every couple of years. Arnie showed a graph
that was pretty amazing. It essentially was a graph of the number
of transistors on a chip over the years. The graph was split into
five eras. The names of the eras are instructive. The Medium
Scale Integration (MSI) era began in about 1969 with a couple
thousand transistors on a chip. By 1972, the Large Scale
Integration (LSI) era had begun with tens of thousands of
transistors per chip. The decade beginning in 1980 was the Very
Large Scale Integration (VLSI) era of a few million per chip.
When I retired from Bell Labs, I taught a graduate course at
Rutgers using a book titled "VLSI Technology". The decade
beginning in 1990 was the Ultra Large Scale Integration (ULSI)
era, with tens of millions of transistors on a chip. Now, with the
advent of the 21st century, we''re in the Giga Scale Integration
(GSI) era heading for a billion transistors per chip. If we had a
square chip, and if my math is correct, that comes to over 30,000
rows of over 30,000 transistors in each row - mind boggling!

I''ve mentioned before that there''s a lot of attention being given to
the fact that the transistors are getting so small that the
continuation of Moore''s Law for many more years is in doubt.
One of the many problems with such small devices is one of
Reisman''s ''tolerances'' on the road to smallness. This problem is
based on a simple fact - as you raise the temperature of a silicon
chip, or most anything for that matter, things tend to move
around faster than at ordinary temperatures. This can be a very
good thing. For example, one process used to make silicon
devices is called diffusion. You have an impurity element such
as phosphorus and you feed a vapor containing this impurity over
a hot silicon wafer. The phosphorus diffuses into the hot silicon
and you have the makings of a p-n junction, the basic building
block of most silicon devices. If the silicon wafer were not hot,
the phosphorus would just sit down on the surface and stay there.

A silicon transistor is a structure in which there are different
regions, each containing impurities distributed in a carefully
controlled way. There are typically many steps in the fabrication
and packaging of a device, such as laying down various
insulating layers and metallic layers to conduct the current.
Many of these steps involve heating to high temperatures and
there''s the rub. You have to consider your thermal budget - the
total time you spend at high temperatures. As an example,
suppose you''ve made your transistor and all the impurities are in
the right place.

We''ve said it before but it bears repeating here. A transistor is
not a stable structure, just as diamond is not a stable form of
carbon. It''s like the situation if you carefully take a glass of
water that''s half full and very carefully pour on top some water
with a blue dye in it. If you''re careful enough you have a blue
layer on top of a clear layer. But come back later and the water
will be all one color, a paler blue. Why? Assuming we don''t
have any convection currents or the like, it''s because the dye
wants to distribute itself uniformly throughout the water in the
glass. In the same way, the impurities in the transistor want to
distribute themselves uniformly throughout the silicon. But, if
they did, no more transistor! At ordinary temperatures there''s no
problem. Most impurities diffuse so slowly that the transistor is
stable for years or maybe centuries. But, suppose you have to go
through further processing to make those electrical contacts and
lay down some oxide layers to protect your chip from the
elements? If these processes require high temperatures, you''ve
got to worry. Those impurities can move around.

In the good old days, this wasn''t a problem. There weren''t very
many transistors on a chip and the transistors themselves were
pretty big. If the impurities move around a bit, it wasn''t a big
deal. There were more atoms of impurity around to take up the
slack and your p-n junctions were intact. The silicon industry
has what are called ''design rules''. Design rules relate to the size
of the various features on the silicon chip. If you only have a
few hundred or a few thousand transistors on a chip the design
rule can be pretty large. Reisman gave a couple examples
involving certain impurities and different design rules. In one
example, the design rule was 1 micron. A micron is a millionth
of a meter or about 0.00004 inches. This is much thinner than
most human hair but pretty large by today''s standards. When
you have such large features, it doesn''t matter as much if your
impurities move around a bit. With a design rule of 1 micron,
your thermal budget is a little more than 13 minutes. This is the
maximum time allowed for being at high temperatures.

Now cut your design rule down to 0.125 microns. Your features
are now 8 times smaller. This is more like what today''s silicon
chips are using. Whoops! Reisman calculates your thermal
budget isn''t 13 minutes but only about 13 seconds! Now Moore''s
Law is in trouble. It''s going to take some ingenuity to keep on a
Moore''s Law path. In the old days, the various processes
requiring high temperatures involved pushing and pulling the
chips in and out of furnaces. This involved time to heat the
samples up to temperature and to cool them down. All the while
the atoms of impurities could be on the move. With very small
transistors on a chip, the impurity atoms can''t move very far or
they''re out of the playing field!

With a thermal budget of only 13 seconds, old-fashioned
furnaces are out of the question. The semiconductor industry has
risen to the challenge partly by coming up with new, lower
temperature processes for carrying out some of the fabrication
steps. It also has developed new techniques for rapid heating and
cooling. One, appropriately, is known as "rapid thermal
annealing". In this process, high intensity lamps are flashed on
and off to quickly heat the chip, which cools down rapidly when
the lamp is turned off. Lasers may also be used for the heating
and again the heating and cooling occur rapidly. Maybe Moore''s
Law has some life in it yet.

In the exhibit area at the ECS meeting, I saw my first 1-foot
diameter silicon wafers. These 300-millimeter wafers are in the
process of becoming the new standard for the era of GSI
technology. Coming from a time at Bell Labs when we were
growing silicon crystals the size of my thumb, to see these huge
wafers really knocked my socks off. The wafers on display were
covered with oxide layers of different thicknesses, and were pale
shades of pink, green or yellow depending on the thickness of the
oxide.

I thought back to my departed colleagues, Carl Frosch
and Link Derick. I''ve previously discussed how they came up
with the invention of oxide masking, key to the fabrication of the
integrated circuits on the silicon chip. The invention was
prompted when they saw those same pretty colors on their vastly
smaller silicon wafers in an experiment that failed! I wish they
could have seen that exhibit.

Allen F. Bortrum



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-05/01/2001-      
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Dr. Bortrum

05/01/2001

Thermal Budgets

[Bortrum is on vacation and will return May 15]

Having just filed your tax returns in April, some of you may be
thinking about the need to go on a stricter budget. If so, you''re
not alone. The silicon chip community is and has been quite
concerned about their "thermal budgets" for some time. So, let''s
switch from the ultimate frigidity of recent columns to hotter
stuff. As with the frigid columns, this column was inspired by a
lecture at the recent meeting of The Electrochemical Society
(ECS) in Washington. This was the Solid State Science and
Technology award lecture presented by Arnold Reisman. The
title of his talk was pretty technical but his subtitle was more
down to earth - "The Road to Smallness is Strewn with
Tolerances".

Arnie was one of the first physical scientists hired by IBM back
in 1953 when IBM was setting up their T. J. Watson Research
center in New York City. This was at the beginning of the era of
the semiconductor revolution and I''ve known him for many
decades. In fact, I almost became a colleague of his in IBM''s
then newly built Yorktown Heights research center. During a
brief period of some discontent at Bell Labs, I received an offer
from IBM but turned it down and remained with Bell.

Arnie''s "road to smallness" is the road that has led to the ever
increasing number of transistors on a silicon chip following a law
never passed by a legislative body. That law, of course, is the
famed Moore''s Law that says the number of transistors on the
chip will double every couple of years. Arnie showed a graph
that was pretty amazing. It essentially was a graph of the number
of transistors on a chip over the years. The graph was split into
five eras. The names of the eras are instructive. The Medium
Scale Integration (MSI) era began in about 1969 with a couple
thousand transistors on a chip. By 1972, the Large Scale
Integration (LSI) era had begun with tens of thousands of
transistors per chip. The decade beginning in 1980 was the Very
Large Scale Integration (VLSI) era of a few million per chip.
When I retired from Bell Labs, I taught a graduate course at
Rutgers using a book titled "VLSI Technology". The decade
beginning in 1990 was the Ultra Large Scale Integration (ULSI)
era, with tens of millions of transistors on a chip. Now, with the
advent of the 21st century, we''re in the Giga Scale Integration
(GSI) era heading for a billion transistors per chip. If we had a
square chip, and if my math is correct, that comes to over 30,000
rows of over 30,000 transistors in each row - mind boggling!

I''ve mentioned before that there''s a lot of attention being given to
the fact that the transistors are getting so small that the
continuation of Moore''s Law for many more years is in doubt.
One of the many problems with such small devices is one of
Reisman''s ''tolerances'' on the road to smallness. This problem is
based on a simple fact - as you raise the temperature of a silicon
chip, or most anything for that matter, things tend to move
around faster than at ordinary temperatures. This can be a very
good thing. For example, one process used to make silicon
devices is called diffusion. You have an impurity element such
as phosphorus and you feed a vapor containing this impurity over
a hot silicon wafer. The phosphorus diffuses into the hot silicon
and you have the makings of a p-n junction, the basic building
block of most silicon devices. If the silicon wafer were not hot,
the phosphorus would just sit down on the surface and stay there.

A silicon transistor is a structure in which there are different
regions, each containing impurities distributed in a carefully
controlled way. There are typically many steps in the fabrication
and packaging of a device, such as laying down various
insulating layers and metallic layers to conduct the current.
Many of these steps involve heating to high temperatures and
there''s the rub. You have to consider your thermal budget - the
total time you spend at high temperatures. As an example,
suppose you''ve made your transistor and all the impurities are in
the right place.

We''ve said it before but it bears repeating here. A transistor is
not a stable structure, just as diamond is not a stable form of
carbon. It''s like the situation if you carefully take a glass of
water that''s half full and very carefully pour on top some water
with a blue dye in it. If you''re careful enough you have a blue
layer on top of a clear layer. But come back later and the water
will be all one color, a paler blue. Why? Assuming we don''t
have any convection currents or the like, it''s because the dye
wants to distribute itself uniformly throughout the water in the
glass. In the same way, the impurities in the transistor want to
distribute themselves uniformly throughout the silicon. But, if
they did, no more transistor! At ordinary temperatures there''s no
problem. Most impurities diffuse so slowly that the transistor is
stable for years or maybe centuries. But, suppose you have to go
through further processing to make those electrical contacts and
lay down some oxide layers to protect your chip from the
elements? If these processes require high temperatures, you''ve
got to worry. Those impurities can move around.

In the good old days, this wasn''t a problem. There weren''t very
many transistors on a chip and the transistors themselves were
pretty big. If the impurities move around a bit, it wasn''t a big
deal. There were more atoms of impurity around to take up the
slack and your p-n junctions were intact. The silicon industry
has what are called ''design rules''. Design rules relate to the size
of the various features on the silicon chip. If you only have a
few hundred or a few thousand transistors on a chip the design
rule can be pretty large. Reisman gave a couple examples
involving certain impurities and different design rules. In one
example, the design rule was 1 micron. A micron is a millionth
of a meter or about 0.00004 inches. This is much thinner than
most human hair but pretty large by today''s standards. When
you have such large features, it doesn''t matter as much if your
impurities move around a bit. With a design rule of 1 micron,
your thermal budget is a little more than 13 minutes. This is the
maximum time allowed for being at high temperatures.

Now cut your design rule down to 0.125 microns. Your features
are now 8 times smaller. This is more like what today''s silicon
chips are using. Whoops! Reisman calculates your thermal
budget isn''t 13 minutes but only about 13 seconds! Now Moore''s
Law is in trouble. It''s going to take some ingenuity to keep on a
Moore''s Law path. In the old days, the various processes
requiring high temperatures involved pushing and pulling the
chips in and out of furnaces. This involved time to heat the
samples up to temperature and to cool them down. All the while
the atoms of impurities could be on the move. With very small
transistors on a chip, the impurity atoms can''t move very far or
they''re out of the playing field!

With a thermal budget of only 13 seconds, old-fashioned
furnaces are out of the question. The semiconductor industry has
risen to the challenge partly by coming up with new, lower
temperature processes for carrying out some of the fabrication
steps. It also has developed new techniques for rapid heating and
cooling. One, appropriately, is known as "rapid thermal
annealing". In this process, high intensity lamps are flashed on
and off to quickly heat the chip, which cools down rapidly when
the lamp is turned off. Lasers may also be used for the heating
and again the heating and cooling occur rapidly. Maybe Moore''s
Law has some life in it yet.

In the exhibit area at the ECS meeting, I saw my first 1-foot
diameter silicon wafers. These 300-millimeter wafers are in the
process of becoming the new standard for the era of GSI
technology. Coming from a time at Bell Labs when we were
growing silicon crystals the size of my thumb, to see these huge
wafers really knocked my socks off. The wafers on display were
covered with oxide layers of different thicknesses, and were pale
shades of pink, green or yellow depending on the thickness of the
oxide.

I thought back to my departed colleagues, Carl Frosch
and Link Derick. I''ve previously discussed how they came up
with the invention of oxide masking, key to the fabrication of the
integrated circuits on the silicon chip. The invention was
prompted when they saw those same pretty colors on their vastly
smaller silicon wafers in an experiment that failed! I wish they
could have seen that exhibit.

Allen F. Bortrum